An information processing device adopting a multi CPU system having a plurality of central processing units (CPUs) as arithmetic processing units performs error detection of data in data transmission and reception between chips (e.g., LSIs) as semiconductor devices provided on a board thereof. Thus, reliability of the multi CPU system is improved. Also, the information processing device adopting the multi CPU system collects history information of the transmission and reception of the data to analyze. Thus, serious breakdown and failure are prevented and maintenance is rapidly performed against the breakdown.
Meanwhile, in a computer-to-computer data distributing system, there is proposed trace executing means and the like to trace a data packet transmitted over a network when receiving trace start request from a transmission side computer until receiving a trace stop notification.
Also, in a private exchange device capable of performing a packet trace of a specified line, there is proposed maintenance operation means and the like for receiving a packet trace registration request command and a packet trace data output request command from input/output means.
Also, as a trace method, there is proposed a trace method to select a type of data from a plurality of types of data generated by executing a predetermined function to collect data of a selected type as a trace target.
Further, in a large-scale system, there is proposed holding means and the like for holding partition information used for an interface to which a crossbar device is connected in each of a plurality of ports for connection to the outside in the crossbar device.
FIGS. 7 and 8 are views for illustrating a process of a history function which was studied by the present inventor. Hereinafter, the process of the history function in the information processing device of the multi CPU system having a plurality of system boards #0 and #1, a crossbar board, and a chip management board is described.
FIG. 7 is a view illustrating operation timing of the history function of the information processing device in an example in which a CPU #3 of the system board #1 requests to read a memory of the system board #0, and thereafter a CPU control chip of the system board #1 transmits a packet to the system board #0.
In FIG. 7, (za) is an example of timing to activate a power supply of the information processing device, and (zb) and (zc) are examples of timing to issue activation and deactivation of the history function from the chip management board. Also, (zd) to (zh) are examples of operation timing of the history function of each chip.
Assume that an error of the data occurs in a main bus of the information processing device after activating the power supply (a rising edge of a square wave) of the information processing device (za). When a user recognizes the error, the user performs an error analyzing operation by a personal computer (PC) in order to specify an error cause. In this case, the user recognizes that the packet error is generated in the analyzing operation by the PC, and instructs a chip management board to issue an activation instruction of the history function to each chip via the PC.
The chip management board issues (transmits) the activation instruction of the history function to the CPU control chip of the system board #1 according to setting of the PC. Subsequently, the chip management board issues the activation instruction of the history function in the order of a memory control chip of the system board #1, a crossbar chip of the crossbar board, a memory control chip, and the CPU control chip of the system board #0 (the rising edge of each square wave in zb).
Each chip, which has received the activation instruction of the history function from the chip management board, activates the history function (the rising edge of the square wave in (zd) to (zh)). That is, each chip stores the history information such as a destination, a recipient, a time, and a packet type when transmitting and receiving the packet transmitted and received via the main bus in a memory for history. The chip management board issues (transmits) a deactivation instruction of the history function to each chip when receiving the error detection notification of the packet from any chip, for example, after issuing the activation instruction of the history function (the rising edge of each square wave in (zc)). Meanwhile, the memory for history is generally the memory of a small capacity. Therefore, for example, until the instruction of the activation stop is issued, each chip rewrites the memory for history with newest history information when the history information exceeds the capacity of the memory for history to thereby store the newest history information.
FIG. 8 is a view illustrating an example of a process flow of the history function in a case where the CPU control chip of the system board #1 transmits the packet to the system board #0 after the CPU of the system board #1 requests a read instruction of the memory of the system board #0.
The chip management board transmits the activation instruction of the history function to the memory control chip of the system board #0 via a history control wiring (S111). The memory control chip of the system board #0, which receives the activation instruction, activates the history function.
The CPU #3 of the system board #1 performs data request of the memory of the system board #0 (S112). The CPU control chip of the system board #1 transmits the packet to the crossbar chip via the main bus (S113). The crossbar chip transmits the packet to the memory control chip of the system board #0 via the main bus (S114).
The memory control chip of the system board #0 detects the data error of the packet (S115). The memory control chip of the system board #0 notifies the chip management board of the data error via the history control wiring (S116).
In response to the error notification, the chip management board transmits the deactivation instruction of the history function to the memory control chip of the system board #0 via the history control wiring by the chip management unit (S117). The memory control chip of the system board #0, which has received the deactivation instruction of the history function, transmits the history information stored in the memory for history to the chip management board (S118).
Meanwhile, although not described above, assume that the chip management board also issues the activation and deactivation instructions of the history function to other chips via the history control wiring as in the above-described case to collect the history information. According to this, the user may access the history information collected by the chip management board via the PC and use the collected history information to analyze a cause of the error occurrence of the information processing device.
However, according to the study by the present inventor, the chip management board notifies each chip of the activation and deactivation instructions of the history function of each chip via the history control wiring to control in the process of the history acquisition illustrated in FIGS. 7 and 8. Therefore, the following problem occurs.
In the information processing device which has been studied by the present inventor, the chip management board issues the activation or deactivation instruction of the history function to the chip, which collects the history information, via the history control wiring, in order to collect the history information. Each chip, which has received the instruction, starts or stops acquiring the history information. As illustrated in FIG. 7, the chip management board individually issues the above-described instruction to each chip via the history control wiring, so that a time difference in timing of the activation and deactivation of the history function between each chip becomes large.
For example, according to the study by the present inventor, a speed of communication used in serial communication using the history control wiring as a medium is approximately several hundred kbps. Therefore, the time difference occurs in reception timing of the instruction of the history function from the chip management board to each chip via the history control wiring being a low-speed signal interface between the chips. The time difference is significant when the communication speed of the main bus is approximately several hundred Mbps or higher. Since the history information collected by the chip management board from each chip is acquired during a time period between the activation and the deactivation of the history function by each chip, an information amount of the history information of the same period of time becomes smaller due to the time difference. That is, the history information of the same period of time used for specifying the error cause is smaller. As a result, when some error occurs in the information processing device and the error cause is specified via the PC, since the information amount of the collected history information is not sufficient, the user may require much effort to perform analyses and so on.